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HV582
HV582
Advance Information
96-Channel AC Plasma Display Data Driver with High Voltage Push-Pull Outputs
Features
HVCMOS(c) technology Operating output voltage of 90V Data clock speed 30MHz @ VDD=5V Six interleaved inputs and outputs Data directional loading control Outputs: enable, polarity, all Hi, all Lo CMOS compatible inputs
General Description
The HV582 is a low voltage to high voltage converter with 96 high voltage push-pull outputs. This device has been designed to operate as a data driver for AC plasma display panels. The device is loaded at up to 30MHz using six parallel data inputs, achieving an effective 180MHz data load rate. A direction pin (DIR) is provided to control the data load sequence. Once data is latched into the output latches, the outputs will be controlled based on the latch contents, polarity (POL) pin and output enable (OE) pin inputs. All outputs may be temporarily forced high by asserting a `low' on the OHB input. Alternatively, all outputs may be temporarily forced low by asserting a `low' on the OLB input. This versatility allows the outputs to be individually controlled, all set high or low, or all set to a highZ state. Circuitry assures a break-before-make interval when switching the output transistors, preventing output cross-conduction, thereby increasing power efficiency.
Application
AC plasma display data column driver
Functional Block Diagram
6
RGB DIN 6 Shift Registers
6
HVOUT1 Level Translators and HVOUT Buffers HVOUT96
CLK
96-bit Latch
Output Control
RGB DOUT
LE POL OLB OHB OE
09/16/02
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
1
HV582
Absolute Maximum Ratings*
Supply Voltage, VDD Supply Voltage, VPP Logic input levels Ground current High voltage supply current Continuous total power dissipation Operating temperature range Storage temperature range
* All voltages are referenced to device ground.
Ordering Info
Device HV582
* Contact Factory
-0.5V to 6V VDD to 100V -0.5V to VDD+0.5V TBD A TBD A TBD mW -40C to +85C -65C +150C Recommended Operating VPP Max 90V
Package Options Die HV582X
Notes: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. Power-down sequence should be the reverse of the above.
DC Electrical Characteristics (Over operating supply voltages unless otherwise noted)
Symbol
IDD IDDQ IPP IIH IIL RIN VOH VOL VOC IOH
Parameter
VDD supply current Quiescent VDD supply current High voltage supply current High-level logic input current Low-level logic input current Pull-down resistance (DIR, POL, [not]OE, OH, OL) HVOUT High-level output
Data out
Min
Typ
Max
25 100 TBD TBD 1.0 -1.0
Units
mA A mA A A
Conditions
fCLK=30MHz, LE*=LOW All VIN=0V or VDD VPP=90V, all outputs high VPP=90V, all outputs low VIH=VDD VIL=0V
VPP-10 VDD-1 10 1.0
V V V
VPP =90V, IHVOUT=-75mA IDOUT=-4.0mA VDD =5.0V, IHVOUT=75mA IDOUT=-4.0mA IOH=75mA IOL=-75mA VPP=100V
Low-level output HVOUT clamp voltage Output source current
HVOUT
Data out
100
mA
2
HV582
AC Electrical Characteristics (Over operating supply voltages unless otherwise noted)
Symbol
fCLK tW tSU tH tDO tWLE tDLE tSLE tD tR tF tDPOL tDHIZ Clock frequency Clock width high and low Data setup time before clock rises Data hold time after clock rises Delay time for Data Out Width of latch enable pulse LE delay time after rising edge of clock LE setup time before rising edge of clock Delay time for output to start rise/fall Output rise time, 10% to 90% Output fall time, 90% to 10% Delay time for 10% output change from POL Delay time for 10% output change from HI-Z Logic input rise/fall time 15 15 15 TBD 200 200 TBD TBD 5.0 16.5 5.0 15 25
Parameter
Min
Typ
Max
30
Units
MHz ns ns ns ns ns ns ns ns ns ns ns ns ns CL=20pF
Conditions
CL=170pF, VPP=80V CL=170pF, VDD=4.5V
Operating Supply Voltages
Symbol VDD VPP VIH VIL TA Parameter Logic supply voltage, VDD High voltage supply, VPP High-level input voltage Low-level input voltage Operating free-air temperature Min 4.5 60
VDD -
0.9
Typ 5.0
Max 5.5 90 VDD 0.9 +85
Units V V V V C
0 -40
Input and Output Equivalent Circuits
VDD VDD VPP
Input
Data Out
HVOUT
GND Logic Inputs
GND Logic Data Output
GND High Voltage Outputs
3
HV582
Switching Waveforms
DIN tSU tH tWH tWL
CLK tDO
DOUT tDLE tWLE LE tD tSLE
HVOUT
tR/tF
Note: Waveform levels are arbitrary and subject to change.
4
HV582
Functional Block Diagram
VDD GND DRinA VPP 16 bit shirt register D91 D2 16 bit shirt register D92 D3 16 bit shirt register D93 D4 16 bit shirt register D94 D5 16 bit shirt register D95 D6 16 bit shirt register D96 HVGND D1
LD1 Decoder Level Xlator HVout1
DRoutA DGinA
DGoutA DBinA
DBoutA DRinB
96 bit latch
DRoutB DGinB
VPP
DGoutB DBinB CLK DBoutB LE POL OLB OHB OE
Decoder LD96
Level Xlator
HVout96
HVGND
Function Table
Input Function Data All low All high Outputs Hi-Z Invert mode Load S/R Store Data in latches Transparent Mode X X X X
H or L
Outputs POL X X X H L L H L L OLB L H X H H H H H H OHB X L X H H H H H H Shift Reg 1 2...16 * *...* * *...* * *...* * *...* H or L *...* * *...* * *...* L *...* H *...* HV Outputs 1 2...6 L L...L H H...H Z Z...Z * *...* (b) * *...* * *...* * *...* (b) L *...* H *...* Data Out * * * * * * * * *
CLK X X X X
LE X X X L L
OE H H L H H H H H H
X X
X X L H
DIR is direction control: L shifts in CCW direction, QNQN-1; H shifts in CW direction, QNQN+1 Notes: H = high level, L = low level, X = irrelevant,
H H
= low-to-high transition, (b) indicates inversion
* = dependent on previous stage's state before the last CLK or last LE high. 5
HV582
Pad Coordinates
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Function VDD HVGND HVGND VPP VPP VPP HVOUT96 HVOUT95 HVOUT94 HVOUT93 HVOUT92 HVOUT91 HVOUT90 HVOUT89 HVOUT88 HVOUT87 HVOUT86 HVOUT85 HVOUT84 HVOUT83 HVOUT82 HVOUT81 HVOUT80 HVOUT79 HVOUT78 HVOUT77 HVOUT76 HVOUT75 HVOUT74 HVOUT73 HVOUT72 HVOUT71 HVOUT70 HVOUT69 HVOUT68 HVOUT67 HVOUT66 HVOUT65 HVOUT64 HVOUT63 HVOUT62 HVOUT61 HVOUT60 HVOUT59 HVOUT58 HVOUT57 HVOUT56 HVOUT55 Coord -2052, -3892 -2052, -3692 -2052, -3492 -2051, -3293 -2051, -3093 -2051, -2893 -2066, -2705 -2066, -2570 -2066, -2435 -2066, -2300 -2066, -2165 -2066, -2030 -2066, -1895 -2066, -1760 -2066, -1625 -2066, -1490 -2066, -1355 -2066, -1220 -2066, -1085 -2066, -950 -2066, -815 -2066, -680 -2066, -545 -2066, -410 -2066, -275 -2066, -140 -2066, -5 -2066, +130 -2066, +265 -2066, +400 -2066, +535 -2066, +670 -2066, +805 -2066, +940 -2066, +1075 -2066, +1210 -2066, +1345 -2066, +1480 -2066, +1615 -2066, +1750 -2066, +1885 -2066, +2020 -2066, +2155 -2066, +2290 -2066, +2425 -2066, +2560 -2066, +2695 -2066, +2830 Pin 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Function HVOUT54 HVOUT53 HVOUT52 HVOUT51 HVOUT50 HVOUT49 VPP VPP VPP VPP HVGND HVGND HVGND HVGND HVGND HVGND VPP VPP VPP VPP HVOUT48 HVOUT47 HVOUT46 HVOUT45 HVOUT44 HVOUT43 HVOUT42 HVOUT41 HVOUT40 HVOUT39 HVOUT38 HVOUT37 HVOUT36 HVOUT35 HVOUT34 HVOUT33 HVOUT32 HVOUT31 HVOUT30 HVOUT29 HVOUT28 HVOUT27 HVOUT26 HVOUT25 HVOUT24 HVOUT23 HVOUT22 HVOUT21 Coord -2066, +2965 -2066, +3100 -2066, +3235 -2066, +3370 -2066, +3505 -2066, +3640 -2052, +3828 -2052, +4028 -1728, +4028 -1403, +4028 -832, +3884 -632, +3884 -79, +3884 +121, +3884 +686, +3884 +886, +3884 +1457, +4028 +1782, +4028 +2106, +4028 +2106, +3828 +2121, +3640 +2121, +3505 +2121, +3370 +2121, +3235 +2121, +3100 +2121, +2965 +2121, +2830 +2121, +2695 +2121, +2560 +2121, +2425 +2121, +2290 +2121, +2155 +2121, +2020 +2121, +1885 +2121, +1750 +2121, +1615 +2121, +1480 +2121, +1345 +2121, +1210 +2121, +1075 +2121, +940 +2121, +805 +2121, +670 +2121, +535 +2121, +400 +2121, +265 +2121, +130 +2121, -5 Pin 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Function HVOUT20 HVOUT19 HVOUT18 HVOUT17 HVOUT16 HVOUT15 HVOUT14 HVOUT13 HVOUT12 HVOUT11 HVOUT10 HVOUT09 HVOUT08 HVOUT07 HVOUT06 HVOUT05 HVOUT04 HVOUT03 HVOUT02 HVOUT01 VPP VPP VPP HVGND HVGND GND DRINA DGINA DBINA DRINB DGINB DBINB CLK LE RESET GND DIR VDD OHB OLB OE POL DROUTA DGOUTA DBOUTA DROUTB DGOUTB DBOUTB Coord +2121, -140 +2121, -275 +2121, -410 +2121, -545 +2121, -680 +2121, -815 +2121, -950 +2121, -1085 +2121, -1220 +2121, -1355 +2121, -1490 +2121, -1625 +2121, -1760 +2121, -1895 +2121, -2030 +2121, -2165 +2121, -2300 +2121, -2435 +2121, -2570 +2121, -2705 +2106, -2893 +2106, -3093 +2106, -3293 +2106, -3492 +2106, -3692 +2106, -3892 +1650, -4087 +1505, -4087 +1360, -4087 +1215, -4087 +1070, -4087 +925, -4087 +780, -4087 +635, -4087 +490, -4087 +300, -4086 +110, -4085 -80, -4086 -270, -4087 -415, -4087 -560, -4087 -705, -4087 -850, -4087 -995, -4087 -1140, -4087 -1285, -4087 -1430, -4087 -1575, -4087
6
HV582
Pad Layout
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 143 144 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 57 58 59 60 61 62 63 64 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 65 66 67
HV582
92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123
7
HV582
Pin List
Name CLK LE RESET DIR POL OE OLB OHB DRINA, DRINB, DGINA, DGINB, DBINA, DBINB DROUTA, DROUTB, DGOUTA, DGOUTB, DBOUTA, DBOUTB HVOUT1-96 GND VDD HVGND VPP Function Shift register clock Transparent latch enable input Power on reset Shift register direction input Polarity input High impedance control All outputs low All outputs high Description Rising edge triggered L = Hold data, H = Transparent 1 = Resets all shift registers and latches to Low L = CCW, Q96->Q1; H = CW, Q1->Q96 Invert output of latches L = HV output in Hi-Z state, H = normal Active low Active low
Red/green/blue A/B input/output DIR = 0 "input", DIR = 1 "output" Red/green/blue A/B output/input DIR = 0 "output", DIR = 1 "input" High voltage outputs Logic ground Logic power High voltage ground High voltage power
09/16/02rev.2
(c)2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
8
1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 * FAX: (408) 222-4895 www.supertex.com

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